[Home ]   [ فارسی ]  
Main Menu
Home::
Vision::
Mission ::
Goals::
Research Groups::
Publication::
Projects::
Events::
E-Science-Net::
Contact Us::
Facilities::
Published Papers::
::
Forms
..
:: Online Task Scheduling of Dynamically Reconfigurable Architecture: A Latency-Aware Approach ::
 | Post date: 2017/09/9 | 
Online Task Scheduling of Dynamically Reconfigurable Architecture: A Latency-Aware Approach  
Seyed Mehdi Mohtavipour
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
Hadi Shahriar Shahhoseini
School of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran

PDF     │   Abstract   │  Keywords   │  References   │  Cite This

Abstract:
Reconfigurable architectures can take advantage of reconfiguration capability to improve performance and flexibility. Most important parts of these systems, are task scheduling and resource management. As scheduling needs more awareness of resource statues, we propose a novel latency-aware task scheduling by extending decision moments from arrival time to before execution time. The gap time due to waiting times and heavy workload, provides more opportunity to take better decisions and based on it, two service disciplines are used, Earliest Deadline First Service (EDFS) and Highest Speedup First Service (HSFS). We show that latency-aware approach outperforms previously reservation method and in simulation results about 32% improvement are obtained for rejection ratio evaluation metric.

Keywords: Reconfigurable Hardware, FPGA, Scheduling, Workload

References:

[1]T. Pöppelmann, M. Naehrig, A. Putnam, and A. Macias, "Accelerating homomorphic evaluation on reconfigurable hardware", International Workshop on Cryptographic Hardware and Embedded Systems, pp. 143-163, 2015. Google Scholar

[2]  L.I.U. Leibo, W.A.N.G. Dong, C.H.E.N. Yingjie, Z.H.U. Min, Y.I.N. Shouyi, and W.E.I. Shaojun, "An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform", IEICE TRANSACTIONS on Information and Systems, 99(5), pp.1285-1295, 2016.  Google Scholar

[3]  M. Fons, F. Fons, and E. Cantó, "Fingerprint image processing acceleration through run-time reconfigurable hardware", IEEE Transactions on Circuits and Systems II: Express Briefs, 57(12), pp.991-995, 2010. Google Scholar

[4] C. C. Kao, "Performance-oriented partitioning for task scheduling of parallel reconfigurable architectures", IEEE Transactions on Parallel and Distributed Systems, 26(3), pp.858-867, 2015.  Google Scholar

[5]  P. Saha, and T. El-Ghazawi, "A methodology for automating co-scheduling for reconfigurable computing systems", Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign, pp. 159-168, 2007.  Google Scholar

[6]  S. Banerjee, E. Bozorgzadeh, N. Dutt, and J. Noguera, "Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures", Proceedings of the 44th ACM annual Design Automation Conference, pp. 771-776, 2007.  Google Scholar

[7]  H. Liang, S. Sinha, R. Warrier, and W. Zhang, "Static hardware task placement on multi-context FPGA using hybrid  genetic algorithm", IEEE 25th International Conference on Field Programmable Logic and Applications (FPL), pp. 1-8, 2015.  Google Scholar

[8]  T. Marconi, "Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays", Computers & Electrical Engineering, 40(4), pp.1215-1237, 2014.  Google Scholar

[9]  C. Steiger, H. Walder, and M. Platzner, "Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks", IEEE Transactions on computers, 53(11), pp.1393-1407, 2004.  Google Scholar

[10]  Z. Li, K. Compton, and S. Hauck, "Configuration caching management techniques for reconfigurable computing", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 22-36, 2000.  Google Scholar

[11]  Z. Li, and S. Hauck, "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation", Proceedings of the ACM/SIGDA 10th international symposium on Field-programmable gate arrays, pp. 187-195, 2002.   Google Scholar

[12]  Q.H. Khuat, D. Chillet, and M. Hübner, "Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA", NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 1-8, 2014.  Google Scholar

[13]  J.A. Clemente, E.P. Ramo, J. Resano, D. Mozos, and F. Catthoor, "Configuration mapping algorithms to reduce  energy and time reconfiguration overheads in reconfigurable systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(6), pp.1248-1261, 2014.  Google Scholar

[14]  H.S. Shahhoseini, M.M. Bassiri, and S.M. Mohtavipour, "Performance evaluation of reusing based scheduling in on-line reconfigurable computing systems", The CSI Journal on Computer Science and Engineering, Vol. 11, pp. 15-23, 2014.  Google Scholar

 
Cite this paper as:
S. M. Mohtavipour, and H. S. Shahhoseini, 2017, "Online Task Scheduling of Dynamically Reconfigurable Architecture:A Latency-Aware Approach", 2nd International Conference on Electrical Engineering, Allameh Majlesi University, Tehran.
 
View: 117 Time(s)   |   Print: 0 Time(s)   |   Email: 0 Time(s)   |   0 Comment(s)
All Rights reserved
Persian site map - English site map - Created in 0.12 seconds with 47 queries by YEKTAWEB 4212